library IEEE;
use IEEE.std_logic_1164.all;

entity clkUnit is
  
 port (
   clk, reset : in  std_logic;
   enableTX   : out std_logic;
   enableRX   : out std_logic);
    
end clkUnit;

architecture archClk of clkUnit is

begin
    enableRX <= clk when reset = '1' else '0';

    process(clk, reset)
        variable cpt : integer range 0 to 15 := 0;
        begin
            if (reset = '0') then
                enableTX <= '0';
                cpt := 0;
            elsif (clk = '1' and clk'event) then
                cpt := (cpt + 1) mod 16;
                if (cpt = 0) then
                    enableTX <= '1';
                else
                    enableTX <= '0';
                end if;
            end if;
    end process;

end archClk;
